Impulse Tutorial: Generating HDL from C-Language

Overview This Getting Started tutorial demonstrates how to compile a simple digital signal processing (DSP) filter written in C into HDL, ready for FPGA synthesis. The goal of this application will be to generate a 16bit, 12-tap FIR filter as hardware in the form of either VHDL or Verilog. Although this is a relatively simple example in terms of the required lines of C code, it does illustrate some key concepts of Impulse C including the use of streaming and pipelining for high performance. This tutorial covers the basics of C-to-HDL compilation, using a single C-language process. Additional tutorials extend the concepts described in this tutorial and cover desktop simulation and debugging, as well as advanced optimization techniques for increased performance. This tutorial will require approximately 20 minutes to complete, including software run times. Steps Loading the FIR12 Filter Application Understanding the FIR12 Application Compiling the C Code to Create HDL Examining the Generated HDL For additional information about Impulse CoDeveloper, including detailed tutorials describing more advanced design techniques, please visit the Tutorials page at the following location: www.ImpulseAccelerated.com/Tutorials